View UTDA8024_8243806.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

unisonic technologies co., ltd UTDA8024 preliminary linear integrated circuit www.unisonic.com.tw 1 of 15 copyright ? 2015 unisonic technologies co., ltd qw-r113-014.a ic card interface ? description the utc UTDA8024 is analog interface ic for 3v or 5v smart cards. it is placed between the card and the microcontroller to perform communication, control function, all supply and protection functions. it requires very few external components for application. it can be applied in many fields, such as ic card readers for banking, pay tv, ident ification, electronic payment, etc. ? features * three specifically protected hal f-duplex bidirectional buffered i/o lines to card contacts c4, c7 and c8 * automatic activation and deactivation sequences; initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, v dd or v ddp drop-out * 26mhz integrated crystal oscillator * dc/dc converter for v cc generation separately powered from a 5 v 20% supply (v ddp and pgnd) * 3v or 5v 5% regulated card supply voltage (v cc ) with appropriate decoupling has the following capabilities: - i cc <80ma at v ddp =4~6.5v - handles current spikes of 40nas up to 20mhz - controls rise and fall times - filtered overload detectio n at approximately 120ma * built-in debounce on card presence contacts * supply supervisor for spike-killing during power-on and power-off and power-on reset (threshold fixed internally or externally by a resistor bridge) * thermal and short-circuit protection on all card contacts * clock generation for cards up to 20mhz (divided by 1, 2, 4 or 8 through clkdiv1 and clkdiv2 signals) with synchronous frequency changes * non-inverted control of rst via pin rstin * iso 7816, gsm11.11 and emv (payment systems) compatibility * enhanced esd protection on card side (>6kv) * one multiplexed status signal off tssop-28
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 2 of 15 www.unisonic.com.tw qw-r113-014.a ? ordering information ordering number package packing UTDA8024g-p28-r tssop-28 tape reel UTDA8024g-p28-r (1)packing type (2)package type (1) r: tape reel (2) p28: tssop-28 (3) g: halogen free and lead free (3)green package ? marking ? pin configuration clkdiv1 5v/3v pgnd s2 v ddp s1 v up pres i/o aux2 cgnd clk rst v cc poradj cmdvcc rstin v dd gnd off xtal1 i/ouc aux1uc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 clkdiv2 pres aux1 xtal2 aux2uc utc UTDA8024
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 3 of 15 www.unisonic.com.tw qw-r113-014.a ? pin description pin no. pin name description 1 clkdiv1 clk frequency selection input 1 2 clkdiv2 clk frequency selection input 2 3 5v/ v 3 card supply voltage selection input; v cc =5v (high) or v cc =3v (low) 4 pgnd dc/dc converter power supply ground 5 s2 dc/dc converter capacitor; connected between pins s1 and s2; c=100nf with esr<100m ? 6 v ddp dc/dc converter power supply voltage 7 s1 dc/dc converter capacitor; connected between pins s1 and s2; c=100nf with esr<100m ? 8 v up dc/dc converter output decoupling capacit or connection; c=100nf with esr<100mw must be connected between vup and pgnd 9 pres card presence contact input (active low); if pres or pres is active, the card is considered ?present? and a built-in debounc e feature of 8 ms (typ.) is activated 10 pres card presence contact input (active high); if pres or pres is active, the card is considered ?present? and a built-in debounc e feature of 8 ms (typ.) is activated 11 i/o data line to/from card reader contact c7; integrated 11k ? pull-up resistor to v cc 12 aux2 data line to/from card reader contact c8; integrated 11k ? pull-up resistor to v cc 13 aux1 data line to/from card reader contact c4; integrated 11k ? pull-up resistor to v cc 14 cgnd card signal ground 15 clk card clock to/from card reader contact c3 16 rst card reset output from card reader contact c2 17 v cc card supply voltage to card reader contact c1; decoupled to cgnd via 2 100nf or 100+220nf capacitors with esr<100m ? ; note 1 18 poradj power-on reset threshold adjustment input fo r changing the reset threshold with an external resistor bridge; doubles the width of the por pulse when used 19 cmdvcc input from the host to start activation sequence (active low) 20 rstin card reset input from the host 21 v dd supply voltage 22 gnd ground 23 off nmos interrupt output to the host (active low); 20k ? integrated pull-up resistor to v dd 24 xtal1 crystal connection or input for external clock 25 xtal2 crystal connection (leave open-circuit if external clock source is used) 26 i/ouc host data i/o line; integrated 11k ? pull-up resistor to v dd 27 aux1uc auxiliary data line to /from the host; integrated 11k ? pull-up resistor to v dd 28 aux2uc auxiliary data line to/fr om the host; integrated 11 k ? pull-up resistor to v dd note 1. the noise margin on v cc will be higher with the 220nf capacitor
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 4 of 15 www.unisonic.com.tw qw-r113-014.a ? block diagram v dd v ddp s1 s2 21 6 75 poradj 18 off rstin cmdvcc 23 20 19 5v/3v 3 1 2 clkdiv1 clkdiv2 24 25 xtal1 xtal2 aux1uc 27 aux2uc 28 26 i/ouc 22 4 pgnd 8 v up 17 v cc 14 cgnd 16 rst clk 15 pres 10 9 pres 13 aux1 12 aux2 11 i/o supply internal reference v ref voltage sense alarm power_on dc/dc converter internal oscillator 2.5 mhz en1 clkup en2 pv cc v cc generator en5 rst buffer gnd horseq clock circuitry clk sequencer en4 buffer clock en3 oscillator thermal protection i/o transceiver i/o transceiver i/o transceiver
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 5 of 15 www.unisonic.com.tw qw-r113-014.a ? absolute maximum rating parameter symbol ratings unit supply voltage v dd -0.3~+6.5 v dc/dc converter supply voltage v ddp -0.3~+6.5 v voltage on input and output pins pins xtal1, xtal2, 5v/ v 3, rstin, aux1uc, aux2uc, i/ouc, clkdiv1, clkdiv2, cmdvcc , off and poradj v i , v o -0.3~+6.5 v voltage on card pins pins pres, pres , i/o, rst, aux1, aux2 and clk v card -0.3~+6.5 v voltage on other pins pins v up , s1 and s2 v n -0.3~+6.5 v card contacts in typical application (note 2) pins i/o, rst, v cc , aux1, aux2, clk, pres and pres -6~+6 kv human body model -2~+2 kv electrostatic discharge voltage all pins (note 2) machine model v esd -200~+200 v maximum junction temperature t j(max) 150 c storage temperature t stg -55~+150 c notes: 1. absolute maximum ratings are those values beyond which the device could be permanently damaged. absolute maximum ratings are stress ratings only and functional device oper ation is not implied. 2. all card contacts are prot ected against any short-circuit with any other card contact. ? thermal resistance s characteristics parameter symbol ratings unit junction to ambient in free air ja 100 k/w
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 6 of 15 www.unisonic.com.tw qw-r113-014.a ? electrical characteristics v dd =3.3v; v ddp =5v; t amb =25c; f xtal =10mhz; all currents owing into the ic are positive; see note 1; unless otherwise speci ed. parameter symbol test conditions min typ max unit temperature ambient temperature t amb -25 +85 c supplies supply voltage v dd 2.7 6.5 v v cc =5v, cc i <50ma 4.0 5.0 6.5 v dc/dc converter supply voltage v ddp v cc =5v, cc i <20ma 2.5 6.5 v card inactive 1.2 ma supply current i dd card active, f clk =f xtal , c l =30pf 1.5 ma inactive mode 0.1 ma active mode, f clk =f xtal , c l =30pf, cc i=0 10 ma v cc =5v, cc i =80ma 200 ma dc/dc converter supply current i ddp v cc =3v, cc i =65ma 100 ma falling threshold voltage on v dd v th2 no external resistors at pin poradj, v dd level falling 2.35 2.45 2.55 v hysteresis of threshold voltage v th2 v hys2 no external resistors at pin poradj 50 100 150 mv pin poradj (note 2) external rising threshold voltage on v dd v th(ext)(rise) external resistor bridge at pin poradj, v dd level rising 1.240 1.28 1.310 v external falling threshold voltage on v dd v th(ext)(fall) external resistor bridge at pin por adj, v dd level falling 1.190 1.22 1.26 v hysteresis of threshold voltage v th(ext) v hys(ext) external resistor bridge at pin por adj 30 60 90 mv hysteresis of threshold voltage v th(ext) variation with temperature ? v hys(ext) external resistor bridge at pin poradj 0.25 mv/k no external resistors at pin poradj 4 8 12 ms width of internal power-on reset pulse t w external resistor bridge at pin poradj 8 16 24 ms v poradj <0.5v -0.1 4 10 a leakage current on pin poradj i l(poradj) v poradj >1v -1 +1 a total power dissipation p tot continuous operation, t amb =-25~+85c 0.56 w dc/dc converter clock frequency f clk card active 2.2 3.2 mhz 5v card 5.2 5.8 6.2 v threshold voltage for voltage doubler to change to voltage follower v th(vd-vf) 3v card 3.8 4.1 4.4 v v cc =5v 5.2 5.7 6.2 v output voltage on pin v up (average value) v up(av) v cc =3v, v ddp =3.3v 3.5 3.9 4.3 v
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 7 of 15 www.unisonic.com.tw qw-r113-014.a ? electrical characteristics (cont.) parameter symbol test conditions min typ max unit card supply voltage (pin v cc ) (note 3) external capacitance on pin v cc c vcc note 4 80 400 nf card inactive, cc i=0ma -0.1 0 +0.1 v card inactive, cc i=1ma -0.1 0 +0.3 v card active, cc i <50ma 4.75 5.0 5.25 v card active, single current pulse, i p =-100ma, t p =2ms 4.65 5.0 5.25 v card active, current pulses, i p =40na 4.65 5.0 5.25 v 5v card card active, current pulses, i p =40na with cc i <200ma, t p <400ns 4.65 5.0 5.25 v card inactive, cc i=0ma -0.1 0 +0.1 v card inactive, cc i=1ma -0.1 0 +0.3 v card active, cc i <50ma 2.85 3.0 3.15 v card active, single current pulse, i p =-100ma, t p =2ms 2.76 3.0 3.20 v card active, current pulses, i p =40na 2.76 3.0 3.20 v card supply voltage (including ripple voltage) v cc 3v card card active, current pulses, i p =40na with cc i <200ma, t p <400ns 2.76 3.0 3.20 v ripple voltage on v cc (peak to peak value) v cc(ripple)(p-p) f ripple =20khz~200mhz 350 mv v cc =0~5v 80 ma v cc =0~3v 65 ma card supply current cc i v cc short-circuit to gnd 100 120 150 ma slew rate sr slew up or down 0.08 0.15 0.22 v/s crystal oscillator (pins xtal1 and xtal2) external capacitance on pins xtal1 and xtal2 c xtal1 , c xtal2 depends on type of crystal or resonator used 15 pf crystal frequency f xtal 2 26 mhz frequency applied on pin xtal1 f xtal1 0 26 mhz low-level input voltage on pin xtal1 v il -0.3 +0.3v dd v high-level input voltage on pin xtal1 v ih 0.7v dd v dd +0.3 v
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 8 of 15 www.unisonic.com.tw qw-r113-014.a ? electrical characteristics (cont.) parameter symbol test conditions min typ max unit data lines (pins i/o, i/ouc, au x1, aux2, aux1uc and aux2uc) i/o to i/ouc, i/ouc to i/o falling edge delay t d(i/o-i/ouc) , t d(i/ouc-i/o) 200 ns active pull-up pulse width t pu 100 ns maximum frequency on data lines f i/o(max) 1 mhz input capacitance on data lines c i 10 pf data lines to card reader (pins i/o, au x1 and aux2; with integrated 11k ? pull-up resistors to v cc ) no load 0 0.1 v output voltage v o(inactive) inactive mode i o(inactive) =1ma 0.3 v output current i o(inactive) inactive mode, pin grounded -1 ma i ol =1ma 0 0.3 v low-level output voltage v ol i ol 15ma v cc -0.4 v cc v no dc load 0.9v cc v cc +0.1 v 5 and 3v cards, i oh <-40a 0.75v cc v cc +0.1 v high-level output voltage v oh oh i 10ma 0 0.4 v low-level input voltage v il 0.3 0.8 v high-level input voltage v ih 1.5 v cc +0.3 v low-level input current il i v il =0v 600 a high-level input leakage current lih i v ih =v cc 10 a data input transition time t t(di) v il(max) to v ih(min) 1.2 s data output transition time t t(do) v o =0~v cc , c l 80pf, 10% to 90% 0.1 s integrated pull-up resistor r pu pull-up resistor to v cc 18 k ? current when pull-up active i pu v oh =0.9v cc , c=80pf -1 ma data lines to microcontroller (pins i/ouc, aux1uc and aux2uc; with integrated 11k ? pull-up resistors to v dd ) low-level output voltage v ol i ol =1ma 0 0.3 v no dc load 0.9v dd v dd +0.1 v high-level output voltage v oh 5 and 3v cards, i oh <-40a 0.75v dd v dd +0.1 v low-level input voltage v il -0.3 +0.3v dd v high-level input voltage v ih 0.7v dd v dd +0.3 v high-level input leakage current lih i v ih =v dd 10 a low-level input current l i v il =0v 600 a integrated pull-up resistor r pu pull-up resistor to v cc 18 k ? data input transition time t t(di) v il(max) to v ih(min) 1.2 s data output transition time t t(do) v o =0~v dd , c l <30pf, 10% to 90% 0.1 s current when pull-up active i pu v oh =0.9v dd , c=30pf -1 ma internal oscillator inactive mode 55 140 200 khz frequency of internal oscillator f osc(int) active mode 2.2 2.7 3.2 mhz reset output to card reader (pin rst) no load 0 0.1 v output voltage v o(inactive) inactive mode i o(inactive) =1ma 0 0.3 v output current i o(inactive) inactive mode, pin grounded 0 -1 ma rstin to rst delay t d(rstin-rst) rst enabled 2 s
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 9 of 15 www.unisonic.com.tw qw-r113-014.a ? electrical characteristics (cont.) parameter symbol test conditions min typ max unit i ol =200a 0 0.2 v low-level output voltage v ol i ol =20ma (current limit) v cc -0.4 v cc v i oh =-200a 0.9v cc v cc v high-level output voltage v oh i oh =-20ma (current limit) 0 0.4 v rise time t r c l =100pf, v cc =5 or 3v 0.1 s fall time t f c l =100pf, v cc =5 or 3v 0.1 s clock output to card reader (pin clk) no load 0 0.1 v output voltage v o(inactive) inactive mode i o(inactive) =1ma 0 0.3 v output current i o(inactive) clk inactive, pin grounded 0 -1 ma i ol =200a 0 0.3 v low-level output voltage v ol i ol =70ma (current limit) v cc -0.4 v cc v i oh =-200a 0.9v cc v cc v high-level output voltage v oh i olh =-70ma (current limit) 0 0.4 v rise time t r c l =30pf, note 5 16 ns fall time t f c l =30pf, note 5 16 ns duty factor (except for f xtal ) c l =30pf, note 5 45 55 % slew rate sr slew up or down, c l =30pf 0.2 v/ns control inputs (pins clkdi v1, clkdiv2, cmdvcc, rstin and 5v/3v) (note 6) low-level input voltage v il -0.3 +0.3v dd v high-level input voltage v ih 0.7v dd v dd +0.3 v low-level input leakage current lil i 0 UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 10 of 15 www.unisonic.com.tw qw-r113-014.a ? electrical characteristics (cont.) notes: 1. all parameters remain within limits but are te sted only statistically for t he temperature range. when a parameter is speci ed as a function of v dd or v cc it means their actual value at the moment of measurement. 2. if no external bridge is used t hen, to avoid any disturbance, it is recommended to connect pin 18 to ground. 3. to meet these s pecifications, pin v cc should be decoupled to cgnd using two ceramic multilayer capacitors of low esr both with values of 100nf, or one 100nf and one 220nf (see fig. 6) 4. permitted capacitor values are 100, or 100 + 100, or 220, or 220 + 100, or 330nf. 5. transition time and duty factor definitions are shown in fig.5, 2 1 1 t + t t = 6. pin cmdvcc is active low; pin rstin is active high; for clkdiv1 and clkdiv2 functions see table 1. 7. pin pres is active low; pin pres is active high; pr es has an integrated 1.25a current source to gnd (pres to v dd ); the card is considered present if at least one of the inputs pres or pres is active. table 1 clock frequency selection (note) clkdiv1 clkdiv2 f clk 0 0 8 f xtal 0 1 4 f xtal 1 1 2 f xtal 1 0 f xtal note: the status of pins clkdiv1 and clkdiv2must not be changed simultaneously; a delay of 10ns minimum between changes is needed; the minimum duration of any state of clk is eight periods of xtal1.
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 11 of 15 www.unisonic.com.tw qw-r113-014.a ? timing waveforms
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 12 of 15 www.unisonic.com.tw qw-r113-014.a ? timing waveforms (cont.) cmdvcc rst clk i/o v cc v up t 10 t 12 t 13 t 14 t de fig.3 deactivation sequence t 15 pres off cmdvcc v cc debounce deactivation caused by cards withdrawal deactivation caused by short-circuit debounce fig. 4 behaviour of off, cmdvcc, pres and v cc .
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 13 of 15 www.unisonic.com.tw qw-r113-014.a ? timing waveforms (cont.)
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 14 of 15 www.unisonic.com.tw qw-r113-014.a ? typical application circuit notes: 1. these capacitors must be of the low esr-type and be placed near the ic (within 100mm). 2. utc UTDA8024 and the microcontroller must use the same v dd supply. 3. make short, straight connections between cgnd, c5 and the ground connection to the capacitor. 4. mount one low esr-type 100nf capacitor close to pin v cc . 5. mount one low esr-type 100 or 220nf capacitor close to c1 contact (less than 100mm from it). 6. the connection to c3 should be routed as far from c2, c7, c4 and c8 and, if possible, surrounded by grounded tracks. 7. optional resistor bridge for changing the threshold of v dd . if this bridge is not required pin 18 should be connected to ground.
UTDA8024 preliminary linear integrated circuit unisonic technologies co., ltd 15 of 15 www.unisonic.com.tw qw-r113-014.a utc assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all utc products described or contained herein. utc products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice.

▲Up To Search▲

Price & Availability of UTDA8024

	To Download UTDA8024 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .